1. Field of the Invention
The present invention relates to a method of mounting an electronic part such as a semiconductor chip or a package.
2. Description of the Related Art
The bonding methods for mounting an electronic part, such as a semiconductor chip on a board, are currently divided, roughly, into a method using heat, such as solder reflow or resin cure, and an ultrasonic bonding method. Though different depending on the type of bumps used for bonding, both bonding methods use heat and load (hereinafter referred to “normal bonding”). Taking the effects on a chip into consideration, the conditions for an ideal bonding method include normal temperature, normal pressure and no load. Such a method, however, has not yet been realized.
An almost ideal bonding method has been proposed as a normal-temperature bonding method (hereinafter referred to as “normal-temperature bonding”) using surface activation by Professor Tadatomo Suga, Research Center for Advanced Science and Technology, The University of Tokyo. According to this bonding method, the bonding surfaces are activated and thus can be bonded to each other simply by bringing them into contact with each other under a load. As a result, the bonding at normal temperature becomes possible under almost no load. Various inorganic and organic substances are under study as materials adapted to be bonded at normal temperature.
The normal-temperature bonding, however, requires preprocessing of the bonding surfaces, to make possible the bonding under a light load, by controlling the variations of roughness and height of the bonding surfaces to less than a predetermined level and thus increasing the chance of contact between the bonding surfaces. In an application of the normal-temperature bonding to the bonding of a semiconductor chip to a board, the bonding surfaces are currently preprocessed by CMP (chemical mechanical polishing) or electropolishing of the bumps on a chip, which are made of Au, Cu or the like material. This preprocessing increases both a burden on the chip, and the number of steps, as compared with the preprocessing for the normal bonding. The burden on the chip and the number of steps could both be reduced if the normal-temperature bonding is feasible even without using such severe preprocessing of the bonding surfaces.
Even in the case where the variations of bump roughness and height can be suppressed by the preprocessing of the bonding surfaces, the variations of the surface roughness and height of the board surface terminals still depend on the condition of the board to which the chip is to be bonded. Even bump deformation under a predetermined load, therefore, may not be able to absorb the variations of the gap between the bump bonding surface of the chip and the board surface, and the bonding may end in a failure. Applying an unnecessary heavy pressure to absorb the variations would damage the chip and the board. A similar problem may be posed also in the case where a package is mounted on a board.
The conventional method in which a semiconductor chip and a board are bonded to each other by normal-temperature bonding is described in Japanese Unexamined Patent Publications No. 2002-50861 and No. 2002-373913 (JP 2002-50861 A and JP 2002-373913 A). JP 2002-50861 A discloses a method of bonding an electronic part such as a semiconductor chip to a circuit-forming member such as a board by normal-temperature bonding using Au, Cu, Al, In or Sn as a material of a connector between the electronic part and the circuit-forming member. JP 2002-373913 A discloses a technique in which one electronic part having bonding sites provided with an indium layer and the other electronic part having connection terminals formed of a metal such as gold or copper at corresponding bonding sites are bonded to each other at the bonding sites at normal temperature in an electrolytic solution or a reducing solution.